Arteris Inc.

12/19/2024 | Press release | Archived content

Semiconductor Engineering: 2024 Set The Stage For NoC Interconnect Innovations In SoC Design

The year's advancements in modular scaling, cache coherence, and hardware/software integration.

What a year it's been for Arteris! Reflecting on 2024, the company achieved exciting milestones and breakthroughs that pushed the boundaries of system-on-chip (SoC) design. A game-changing new technology was unveiled, a major product was launched, and existing solutions were tailored for AI, automotive, high-performance computing (HPC) and more.

Along the way, we welcomed new partners and deepened relationships with existing ones, strengthening collaborations that drive progress. By staying closely connected with customers, our engineers delivered practical solutions to address the ever-evolving challenges of modern SoC design.

Ecosystem expansion

Partnerships were a highlight of 2024, showcasing Arteris' reach across the semiconductor ecosystem. Among the many relationships the company cultivated, we strengthened ties with IP providers like Andes Technology, MIPS and SiFive, worked with chipmakers such as Tenstorrent, EdgeQ and Rain AI, and expanded our partnership with Arm. Support for VeriSilicon with its one-stop custom silicon services also continued to grow. These examples represent just a portion of the partnerships driving innovation and progress across our industry as we remain committed to advancing RISC-V, AI, edge computing, and SoC design success.

Technology advancements

This year, groundbreaking NoC soft tiling capabilities were introduced within Arteris' FlexNoC and Ncore interconnect IPs. This transformative approach enables SoC architects to partition chips into modular, self-contained units, allowing seamless scaling of compute performance to meet evolving demands. An additional benefit is its support for derivative design, which allows pre-verified soft tiles to be reused across multiple SoCs, significantly reducing development time. In some cases, this approach has achieved up to a 50% reduction.

To read the full article on Semiconductor Engineering, click here.