How hyperscale computing works.

The power problem goes beyond the data center. Power efficiency is a consideration across every layer of silicon and semiconductor technology. Better transistors can deliver more computation with less energy. Process innovations like RibbonFET gate-all-around transistors and PowerVia backside power delivery improve performance per watt in different ways. RibbonFET improves electrostatic control and supports more efficient performance scaling, while PowerVia improves transistor control and power delivery by moving power routing to the back of the die, freeing up front-side real-estate for signal routing and reducing power-delivery congestion.

Advanced packaging innovations also allow for greater transistor density, so architects can overcome the physical limits of how large a single die can practically be. Building every function into one enormous piece of silicon doesn't always make sense.

The alternative is disaggregation, where functions are built as separate pieces of silicon, called chiplets, and combined in the same package. That only works if the pieces can exchange data extremely quickly and efficiently, which is where packaging technologies like Embedded Multi-die Interconnect Bridge (EMIB) and Foveros Direct 3D come in, connecting multiple dies at high densities.

Intel's next generation server processor, codenamed Diamond Rapids, demonstrates this approach with unified memory fabric, built with Foveros Direct 3D packaging and UCIe-S die-to-die interconnect. This shift, where the package itself is a critical part of the computing architecture, is necessary for delivering scalable, power-efficient compute.