Early Research Demonstrated Novel Approach to Next-Generation Transistor Design

As the microelectronics industry moves to adopt gate-all-around transistor designs in next-generation smartphones, groundbreaking research from nearly 20 years ago at Lawrence Berkeley National Laboratory (Berkeley Lab) demonstrated an innovative approach to creating these advanced structures.

The technology - called gate-all-around field-effect transistors (GAA-FET) - represents a key architectural advance for packing billions more transistors into the tiny microchips that are found in smartphones and laptops. The "gate-all-around" design enhances control over the transistor channel, leading to better performance and lower power consumption. While industry is now implementing GAA-FET through traditional top-down fabrication, Berkeley Lab's early bottom-up approach showed the potential of this geometry using chemical synthesis to achieve these complex structures.

"I'm pleased to see the continued evolution of transistor architectures in the semiconductor industry," said Peidong Yang, who published work on bottom-up synthesis of gate-all-around structures in a pioneering paper in 2006. "Our early exploration of chemical synthesis approaches to creating complex transistor geometries demonstrated alternative pathways for fabricating these structures." Yang is a faculty senior scientist in Berkeley Lab's Materials Sciences Division and a professor of chemistry and materials science and engineering at UC Berkeley.

Transistors are the fundamental building blocks of modern computing - and some of the best-performing microchips in smartphones today consist of more than 10 billion of them, each just 5 nanometers in size. Each transistor acts like a switch, allowing or blocking the flow of current through a semiconductor channel, enabling the binary operations that underpin modern computing.

A transistor's gate is the control input that determines whether the transistor is on or off. For the past decade, the most common transistor design was the FinFET (Fin Field-Effect Transistor), which positioned the semiconductor channel vertically, like a fin on a tiny surfboard, with the gate wrapping around it on three sides. Shrinking the FinFET below 5 nanometers, however, reduces gating and energy efficiency.

Microchip manufacturers want to continue pushing the limits of Moore's Law by packing tens of billions more transistors into a chip no bigger than the size of a fingernail. A higher transistor density would require even smaller transistors - down to 2 nanometers (the size of a DNA strand) or, more ambitiously, the size of a few silicon atoms (1 nanometer). Smaller chips means smaller devices and can also make chips more energy-efficient.

The microelectronics industry has known for decades that the gate-all-around approach - a design concept that wraps the gate all the way around the channel - could potentially make a higher-performing, more efficient transistor at sub-5-nanometer scales. While traditional top-down lithography faced technical challenges in fabricating GAA-FET geometries in the early 2000s, researchers were exploring various approaches and structures to realize this design concept.

In a scientific first, the Yang group demonstrated an unconventional bottom-up approach to creating silicon-based, gate-all-around transistors using chemical vapor deposition (CVD). In their seminal 2006 paper in Nano Letters, "Silicon Vertically Integrated Nanowire Field Effect Transistors," Yang and team used CVD to grow vertical silicon nanowires coated with an ultrathin metallic layer and embedded in silicon dioxide. This achieved a gate-all-around structure using industry-standard materials, but through chemical synthesis rather than traditional lithography.