How GM “breaks” camera streams on purpose to help build safer vehicles

By Mayank Rai, Engineering Group Manager - CCU Kernel, GM Infotainment Product Development

As GM accelerates toward software-defined vehicles and increasingly camera-dependent safety features, the reliability of our entire camera pipeline - spanning lenses, sensors, and on-vehicle image processing-has never been more critical. High-quality image data underpins features such as surround view, interior monitoring, and future automated driving capabilities, making it foundational to both vehicle safety and the customer experience.

Yet one of the most persistent challenges in camera development has been reproducing real-world faults-the rare, intermittent issues that occur only under specific electrical, environmental, or timing conditions. These issues are often nearly impossible to recreate in the lab, making debugging lengthy, inconsistent, and heavily dependent on vehicle testing.

To solve this, our Camera Platform team has developed a Field-Programmable Gate Array (FPGA)-based Mobile Industry Processor Interface (MIPI) Fault Injection platform. The FPGA-based MIPI Fault Injection system gives GM a new internal capability for precise, automated, and repeatable fault injection in MIPI camera serial interface 2 (CSI-2) camera data streams. It's already helping us validate diagnostics, accelerate root-cause investigations, and significantly improve product quality across multiple vehicle programs.

Why fault injection matters

Cameras are extremely sensitive electronic systems. Small anomalies-such as a corrupted packet, a dropped line, or a momentary coax disturbance-can ripple through downstream processing and affect perception algorithms or viewing experiences.

Compounding the challenge is that most real sensors cannot intentionally generate faults such as frozen frames or truncated payloads or coax open/short conditions.

Without a controlled way to inject such errors, engineers are forced to rely on chance: waiting for a vehicle to hit the right conditions, recreating environmental stress, or physically manipulating cables to trigger faults. These methods are slow, inconsistent, and costly.

Our team set out to change that.

Building a new system

To enable testing of deliberately induced errors, the GM team engineered a custom Verilog-based fault injection module running on the Ultra96-V2 FPGA (Zynq UltraScale+ MPSoC). Acting as a fully programmable virtual camera, the FPGA generates valid MIPI CSI-2 video streams and can inject precise, targeted faults or random errors-performing full fuzz testing to rigorously validate the camera subsystem's resilience and fault detection.

The system can inject:

• Cyclic-redundancy check (CRC) errors
• Error correcting code (ECC) header errors
• Missing End of line (EOL)/End of frame (EOF) markers
• Dropped or truncated lines
• Frozen frames
• Embedded-line corruption
• Pixel-stream manipulations
• Open/short/noise faults via a companion shield board

Faults are triggered via simple Inter-Integrated Circuit (I²C) commands from the Central Compute Unit (CCU), enabling complete automation. This means test scenarios can be reproduced exactly, down to the frame number.

The entire pipeline-from FPGA output to system-on-chip (SoC) to camera software development kit (SDK)-can now be tested with known, intentionally induced faults, giving us clear visibility into how the system behaves under stress.

How it works (high-level)

The FPGA-based fault injection system interfaces with the Device Under Test (DUT), which is the CCU/virtual cockpit unit (VCU), and behaves like a production camera connected over the same hardware interface. The FPGA generates well-controlled MIPI camera frames, while the DUT configures the fault injection system over I²C as part of its test cases. Based on these commands, the FPGA injects specific MIPI-level faults directly into the video stream, enabling validation of both hardware and software behavior under fault conditions.

This gives GM unprecedented control to systematically stress, observe, and validate the entire camera pipeline with precision and repeatability.

FPGA system logic

At a high level, the FPGA implements a complete video generation and MIPI transmission pipeline, with GM-owned IP responsible for injecting protocol-correct faults in real time.

The diagram above illustrates the FPGA logic architecture used in the fault injection system. Most IP blocks are connected through an Advanced eXtensible Interface (AXI) interconnect and are configured by the processing system (PS). The PS consists of a hard ARM processor and handles initialization, configuration, and control of the programmable logic (PL).

The PL implements the complete video generation and MIPI transmission pipeline. A Video Timing Controller (VTC) IP block is used to generate the required video timing signals. A Test Pattern Generator (TPG) produces video patterns in the desired color format. The AXI-to-Video converter applies the timing information from the VTC to the generated pixel data, introducing synchronization signals such as vertical synchronization (VSYNC) and horizontal synchronization (HSYNC), along with horizontal and vertical back porch and front porch blanking intervals (HBP, HFP, VBP, and VFP). The timing controller helps achieve the target frame rate by precisely controlling these intervals.

The output of the AXI-to-Video converter consists of video data along with the corresponding synchronization signals. This video stream is converted back into an AXI-based video format using a Video-to-AXI bridge. The AXI video stream is then fed into the MIPI CSI-2 transmitter block, which applies the CSI-2 protocol and generates CSI-2 compliant MIPI packets from the video frames.

The output of the MIPI CSI-2 transmitter is intercepted by the MIPI fault injector IP. This is a GM-owned IP responsible for modifying CSI-2 packets to intentionally introduce MIPI-level faults. The fault injector can be configured to inject specific types of errors using control signals driven through general purpose inputs/outputs (GPIO). These GPIOs are configured by the PS via a GPIO controller.

The MIPI fault injector integrates additional logic to support protocol-correct fault injection. An ECC generator IP computes ECC using Hamming code for MIPI short packets, while a line CRC generator computes CRC values for long packets, when needed. The fault injector modifies packet contents in the same clock cycle in which bytes are emitted by the MIPI CSI-2 transmitter, ensuring zero added latency. No further clock delay is introduced as part of fault injection.

The modified MIPI packets are then sent to the D-PHY controller, which transmits the data over the physical D-PHY lanes.

To enable external control, the system implements an I²C slave using an I²C slave IP. This allows the FPGA logic to accept commands from a host system over I²C. Through these commands, the host can start or stop MIPI streaming and specify the types of MIPI faults that the FPGA system should inject during operation.

The impact for GM

By bringing fault injection into a controlled, FPGA-driven lab environment, GM's teams can now stress-test the entire camera pipeline with a level of precision that was previously impossible. This capability is already changing how we validate, debug, and scale camera features. It's also driving measurable gains and strengthening our long-term readiness, through:

1. Significantly improved product quality

With the ability to create faults on demand, teams can now:

• Validate diagnostic code paths thoroughly
• Test boundary and corner cases previously considered "unreachable"

This leads to stronger, more predictable camera behavior across viewing and advanced driver assistance systems (ADAS) features.

2. Faster debugging cycles

What previously required repeated vehicle tests or environmental triggers can now be reproduced in seconds. This dramatically reduces time spent on:

• Field return analysis
• Hard-to-reproduce issues
• Camera Pipeline instability investigations
• Integration testing

The result is a faster path to root cause and quicker resolutions for engineering teams.

3. Reduced cost and resource usage

By shifting fault reproduction from vehicles to the lab, we reduce:

• Time spent on vehicle-level testing
• Dependence on external equipment
• Manual coax manipulation and physical stress tests
• Costly environmental chamber runs
• Cycles lost waiting for rare faults to happen spontaneously

The platform consolidates an entire class of testing into a predictable, lab-based workflow. This transforms camera fault validation from an opportunistic activity into a planned, efficient software-defined vehicle lab workflow.

4. GM's increasing technical independence

Most suppliers do not provide fault injection tools at this level. By developing our own, we gain:

• Internal ownership of critical validation capability
• The ability to test camera pipelines earlier and more thoroughly
• Independence from sensor vendor limitations
• A platform aligned with GM's strategy of owning key software assets

This strengthens our technical foundation and reduces reliance on external development timelines.

5. A scalable foundation for the future

The platform is designed to evolve with upcoming needs:

• Multi-lane, high-bandwidth cameras
• More complex embedded metadata
• Functional safety-oriented test sets
• Next-generation serializers and deserializers
• Advanced ADAS use cases

This investment pays long-term dividends across our next-gen SDV platform and beyond.

Driving innovation and exceptional quality

With the FPGA-based MIPI Fault Injection system, GM gains a powerful new way to validate, debug, and harden camera-driven features. It ensures that the camera pipelines underpinning our next generation of software-defined vehicles behave predictably-even under corrupted data-and that our diagnostics are prepared for real-world issues long before vehicles reach customers.

It also reinforces GM's broader shift toward internal engineering ownership, deeper technical understanding, and proactive quality assurance-underscoring a core theme we're driving across the organization: innovation that directly enhances product quality.