Solving AI's Data Movement Problem: A Conversation with Eliyan

October 21, 2026

As AI systems grow past a single chip into racks of processors that must operate as one, the benchmark of performance has moved from how fast chips compute to how fast data moves.

Eliyan, founded in Santa Clara in 2021 by Ramin Farjadrad, Syrus Ziai, and Patrick Soheili, builds the interconnect for that problem, from chiplet links to optics built on micro-VCSEL arrays. In July, the company closed a $145 million Series C at a $1 billion valuation. Celesta is proud to have backed Eliyan since its Series A.

In this conversation, Co-Founder and CEO Ramin Farjadrad explains why the memory, I/O, and power wall challenges are converging, how custom HBM and VCSEL optics address it, and what the new round will fund.

As AI systems grow past a single chip into racks of processors that must operate as one, the benchmark of performance has moved from how fast chips compute to how fast data moves.

Eliyan, founded in Santa Clara in 2021 by Ramin Farjadrad, Syrus Ziai, and Patrick Soheili, builds the interconnect for that problem, from chiplet links to optics built on micro-VCSEL arrays. In July, the company closed a $145 million Series C at a $1 billion valuation. Celesta is proud to have backed Eliyan since its Series A.

In this conversation, Co-Founder and CEO Ramin Farjadrad explains why the memory, I/O, and power wall challenges are converging, how custom HBM and VCSEL optics address it, and what the new round will fund.

‍For readers hearing about Eliyan for the first time, what is your technology addressing?

We build the connections that move data through an AI data center: die-to-die links between chiplets in the same package, interfaces between processors and memory, chip-to-chip links across a tray, and optical links between racks.

Our goal is to overcome two major constraints: the memory wall, which limits how quickly processors can access enough data, and the I/O wall, which limits communication between processors. The copper wall is a growing part of that I/O challenge, as electrical links reach practical limits in bandwidth, reach, and power.

Why has data movement become such a big bottleneck?

When we started Eliyan in 2021, the industry was already adopting high-bandwidth memory because many AI workloads were constrained by how quickly data could get into and out of the processor. Even with HBM attached, memory-bound workloads can use only a fraction of a GPU's available compute. Adding more processing capability does little if you cannot keep it fed.

At the same time, transistor scaling became slower and more expensive. Designers expanded toward reticle-limited dies and then combined multiple compute dies in a package. NVIDIA's progression from multi-die GPUs to 72-GPU scale-up systems, with larger configurations on its roadmap, illustrates that shift.

The industry now wants hundreds and eventually thousands of processors to work efficiently together. These systems are often described as one giant GPU, but achieving that behavior requires enormous communication bandwidth and low latency. That is the I/O wall.

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"We don't want to chase the ball with the big guys. We want to be where the ball is heading, ahead of time."

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Are the memory, I/O, and power walls separate problems, or one problem?

They are closely interdependent, with data movement a major common driver. Moving data between memory and compute, between chiplets, and across a system consumes power. Increasing bandwidth without improving energy efficiency can quickly make the power problem worse.

Compute throughput has grown much faster than the bandwidth and energy efficiency of the links that feed it. Interconnect used to be good enough. Increasingly, it determines how much useful work the system can deliver.

You proposed custom HBM years before the industry picked it up. What does it change?

Custom HBM opens the memory stack's base die to more advanced logic and interfaces. That allows higher-speed connections to the processor and creates opportunities to move memory-control functions or selected processing closer to the memory.

Our proposal also makes the base die multiport. In architectures that divide the compute die's edges between HBM and I/O, those interfaces compete for limited space. Our dual-port architecture allows the HBM base die to serve both the memory stack and an additional communication path to external I/O chiplets.

That enables HBM to occupy all four edges of the compute die while preserving paths to co-packaged optics or other I/O around it. Depending on the package layout and interface configuration, it can substantially increase both memory and scale-up bandwidth.

The industry is now moving toward custom HBM with more functionality in the base die, as NVIDIA's NVHBM announcement illustrates. That direction aligns with concepts we proposed years ago. Our dual-port architecture extends the idea by enabling memory and scale-up I/O to share the compute die's perimeter.

Optics is the hottest debate in the industry right now. Will optical links replace electrical ones, or will the two coexist long term for different use cases?

They will coexist. Electrical connections remain essential within chips and over short distances. Optics becomes increasingly attractive as bandwidth and reach requirements grow.

Today, optical modules typically connect to processors through high-speed electrical SerDes. Those interfaces are moving toward 200G-class lanes, with 400G-class lanes emerging. As signaling rates increase, maintaining electrical reach at acceptable power becomes harder.

One important direction is to bring the optical engines onto the processor's package and connect them through short die-to-die interfaces. Those shorter connections can significantly reduce electrical interface energy while optics carries the data over longer distances.

What makes Eliyan's optical approach different?

Eliyan pioneered the use of dense 2D microVCSEL arrays-with a pitch below 100 µm-as a practical solution to the copper wall in AI scale-up networks. VCSELs themselves are established technology. Our contribution was the architecture that makes dense 2D arrays viable for high-bandwidth, low-power, reliable communication between AI processors.

As recently as a year ago, this approach faced widespread industry skepticism. We took it to a major hyperscaler and showed how our architecture could address the challenges that had kept it from being considered a viable option: electrical interfaces, optical connectivity, synchronization, reliability, and system integration.

That work helped change the industry's direction. Over the past four to five months, we have seen multiple major interconnect companies shift internal development toward 2D microVCSELs. From our direct engagement with the ecosystem, we believe Eliyan's work was a catalyst for that shift. We identified the opportunity, developed solutions to the difficult architectural problems, and demonstrated a credible path forward before the broader industry embraced it.

Our slow-and-wide architecture distributes bandwidth across many lower-rate optical lanes, reducing the need for power-hungry high-speed signal processing. Dense arrays provide bandwidth density, while spare lanes and repair mechanisms address the reliability requirements of large AI systems. The approach also draws on the manufacturing scale of an established VCSEL ecosystem.

We have now received our Nexus and Oscar chiplets from fabrication, moving our architecture into silicon validation. With foundational IP and a substantial development head start, we are bringing forward a practical optical solution to the copper wall-one that we helped put on the industry's roadmap.

Why did you start Eliyan?

We started Eliyan to solve problems the industry had not yet accepted it would face-and to develop practical solutions before those problems became barriers to growth.

Our team has a long history of doing that, from high-speed Ethernet and chiplet connectivity to new memory and optical architectures. We look several years ahead, identify the physical constraints that will limit progress, and build technologies that can change what is possible.

Our 2D microVCSEL work is a clear example. We pursued it while the industry was focused elsewhere and many dismissed it as impractical. We developed the architecture, addressed the objections, and helped a major hyperscaler see a path to deployment. Now the broader industry is moving toward the direction we pioneered.

As a startup, we win by getting there first with a differentiated, practical solution. We don't want to chase the ball with the big guys. We want to be where the ball is heading, with the technology already developed when the industry arrives.

What goals will your Series C funding help you pursue?

This round will help us turn our technical head start into production deployments and a lasting market position.

We have backing from 12 strategic investors across the AI infrastructure ecosystem, and we have made significant silicon progress across our electrical and optical portfolios. Our priority is to complete validation and qualification, accelerate customer integration, and scale manufacturing.

With 2D microVCSELs, we helped establish a new direction for the industry. The next step is to deliver that architecture at scale: a practical solution to the copper wall that allows AI systems to grow beyond the bandwidth, reach, and power limits of electrical connectivity.

And we will keep innovating. Eliyan's value is both the technology we have developed and the team's ability to anticipate the next constraint and create the next solution.

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