Boise State researcher pushes to make computer memory smarter

For 60 years, computing has run on a simple division of labor: memory chips store data, processors crunch it.

Companies like Micron Technology build the memory, while companies like Intel, AMD and NVIDIA build the processors. It's a model that has powered decades of progress, but has a costly flaw.

"The communication between the processor and the memory becomes the bottleneck," Assistant Professor Purab Sutradhar said. "Every commercially available processor has this bottleneck today, which is masked using clever tricks like adding local cache memory. While this works, it is also inefficient."

The problem comes down to the physics and wiring. Data travels between a memory chip and a processor over a small number of tiny copper connections, typically just eight wires in today's electronics, moving only a single byte at a time.

Sutradhar, who joined the Boise State College of Engineering's Department of Electrical and Computer Engineering in 2024 after earning his Ph.D. at the Rochester Institute of Technology, has spent his career chasing what he calls computing's "elephant in the room." Now, with a new National Science Foundation Engineering Research Initiation (ERI) award, he's building HYDRA - a memory chip that doesn't just store data, but computes with it.

Restructuring processors

One of the viable and highly-effective solutions to the memory bottleneck, Sutradhar explains, is to build computing logic directly into Dynamic Random Access Memory (DRAM), the memory found in virtually every computer and phone. The catch: cramming computing hardware into a device engineered for simplicity and low cost, which introduces new complications.

HYDRA's answer is twofold. First, an intelligent control system lets computing logic and memory operate side-by-side without one interfering with the other, avoiding traffic jams as data moves through the chip. Second, that computing logic is distributed strategically throughout the memory, creating short, localized paths between data and the components processing it, inherently reducing congestion.

Unlike prior designs, where heterogeneity is only skin deep - an AI-specific core here, a general-purpose core there - HYDRA's diversity is built around the physical realities of the memory itself. Compute units inside DRAM's small, high-bandwidth banks are lean and built for massive parallelism. Units outside these banks provide more room but far less bandwidth and handle more complex operations.

Tying these mismatched components together is what Sutradhar calls a "quasi-homogeneous control architecture," hardware that makes wildly different processing units look nearly identical to a programmer, sparing them from having to micromanage the underlying complexity.

Real stakes, real impact

The payoff isn't just theoretical. In earlier research, Sutradhar demonstrated over 22 times greater energy efficiency running advanced encryption standard (AES) encryption on a memory-centric architecture compared to a flagship NVIDIA GPU.

He expects similar gains with HYDRA, not just for standard encryption, but for emerging techniques like fully homomorphic and post-quantum cryptography, alongside multimodal AI workloads that mix text, images, audio and sensor data.

That efficiency matters most for phones, wearables and autonomous systems that need to run AI, process sensor data and secure information, all within a tight power budget. "Any low-power device that requires versatile computing within the same device," Sutradhar said, is a viable candidate to benefit.

Because DRAM's internal design is proprietary and inaccessible to outside researchers, Sutradhar's team will validate HYDRA through a layered simulation strategy before building a field-programmable gate array prototype to confirm the design actually works, bypassing the need to fabricate custom silicon.

Project building a program

For Sutradhar, HYDRA is as much about launching a research career as it is about solving a technical problem. "This funding is crucial for me and my lab beyond the HYDRA project," he said. "The simulation and experimentation setup, the student training, and the preliminary research data will help me build my long-term research and launch new, more advanced projects."

His two-year project will train both doctoral and undergraduate student researchers, and complements his parallel work on 3D-PFLOPS, a related project exploring optical-digital near-memory computing with colleagues Omiya Hassan and Karthik Srinivasan.

Sutradhar also plans to open-source HYDRA's simulation toolchain and bring findings into his course on memory-centric architectures, inviting students and Treasure Valley industry professionals alike to build on the work.

"The traditional computing model is hitting a hard memory wall," Sutradhar said. "The memory-centric computing model is a need of the time." WIth HYDRA, he aims to help make it one.

This material is based upon work supported by the National Science Foundation's Division of Electrical, Communications and Cyber Systems (ECCS) under award No. 2552607. Any opinions, findings and conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the National Science Foundation.

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